Conventionally, an information processing apparatus, such as a server, emulates a CPU (Central Processing Unit) that has architecture different from that of a physical CPU installed in the information processing apparatus. The information processing apparatus also emulates, in addition to the CPU, an OS (Operating System) that is different from an OS installed in the information processing apparatus.
For example, a server equipped with an open source OS, such as LINUX (registered trademark), reproduces a general-purpose OS, which is installed in mainframe, within the own server and runs application or the like for the general-purpose OS.
Such an information processing apparatus not only executes instruction emulation for reproducing an instruction for a different architecture but also executes an interrupt process when any exception occurs. Regarding the interrupt process, for example, Japanese Laid-open Patent Publication No. 58-117059 discloses a technology, in which a status monitoring function, which has been reset every time an interrupt process occurs, is reset only when the reset is needed. Furthermore, Japanese Laid-open Patent Publication No. 62-043737 discloses a technology, in which a PSW (Program Status Word) corresponding to an interrupt process is fixedly stored in a buffer memory that is different form a general buffer memory so that time taken to load the PSW at the time of the interrupt process can be shortened.
When a CPU executes an instruction, information may be overwritten in a PSA (Program Save Area) that is an area of a memory for storing information, such as a PSW corresponding to an interrupt process. Even if the PSA is locked in order to prevent overwriting, when information in the PSA needs to be updated, the lock is released, so that a PSW may be overwritten at the time of the update. In particular, when a memory is shared by a plurality of CPUs, a CPU may overwrite a PSA that is reserved by another CPU.
In this case, a PSW stored in the PSA is rewritten; therefore, a conventional information processing apparatus executes a determination process for determining whether or not a PSW corresponding to an interrupt process contains an error every time an interrupt process occurs. Because the determination process is executed every time an interrupt process occurs, there is a problem in that time taken to execute the interrupt process increases.
In the determination process, whether or not a PSW contains an error is determined by checking values in a plurality of fields in the PSW of 64 bits. For example, when emulating an OS in a 31-bit address mode, an information processing apparatus determines whether bits 24 to 31 are 1 or not. The information processing apparatus also checks a value of each of bit 0, bits 2 and 3, a bit 12, a bit 16, and a bit 17. When all of the bits have normal values, the information processing apparatus executes an interrupt process.
Because the information processing apparatus executes the above determination process every time an interrupt process occurs, when interrupt processes occur frequently, the determination process on the PSW becomes a bottleneck. Therefore, overhead in the interrupt process increases and time taken before a start of the interrupt process increases, resulting in increasing time taken to the interrupt process as a whole.